september 2012 FDMS037N08B n-channel powertrench ? mosfet ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 www.fairchildsemi.com 1 mosfet maximum ratings t a = 25 o c unless otherwise noted* thermal characteristics symbol parameter FDMS037N08B unit v dss drain to source voltage 75 v v gss gate to source voltage 20 v i d drain current - continuous (t c = 25 o c) 100 a - continuous (t c = 25 o c, silicon limited) 128 - continuous (t a = 25 o c) (note 1) 19.9 i dm drain current - pulsed (note 2) 400 a e as single pulsed avalanche energy (note 3) 180.6 mj p d power dissipation (t c = 25 o c) 104.2 w (t a = 25 o c) (note 1) 0.83 w t j , t stg operating and storage temperature range -55 to +150 o c symbol parameter FDMS037N08B unit r jc thermal resistance, junction to case, max. 1.2 o c/w r ja thermal resistance, junction to ambient, max. (note 1) 50 FDMS037N08B n-channel powertrench ? mosfet 75 v, 100 a, 3.7 m features ?r ds(on) = 3.01m (typ.)@ v gs = 10 v, i d = 50 a ? low fom r ds(on) *q g ? low reverse recovery charge, q rr = 80 nc ? soft reverse recovery body diode ? enables highly efficiency in synchronous rectification ? fast switching speed ? 100% uil tested ? rohs compliant description this n-channel mosfet is produced using fairchild semiconductor ? ?s advance powertrench ? process that has been tailored to minimize the on-state resistance while maintain- ing superior switching performance. applications ? synchronous rectification for atx / server / telecom psu ? battery protection circuit ? dc motor drives and uninterruptible power supplies bottom power 56 top d d d d g s s s pin 1 g s s s d d d d 5 6 7 8 3 2 1 4
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 2 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 package marking and ordering information electrical characteristics t j = 25 o c unless otherwise noted off characteristics on characteristics dynamic characteristics switching characteristics drain-source diod e characteristics device marking device package reel size tape width quantity FDMS037N08B FDMS037N08B power 56 13 ? 12 mm 3000 units symbol parameter test conditions min. typ. max. unit bv dss drain to source breakdown voltage i d = 250 a, v gs = 0v 75 - - v bv dss t j breakdown voltage temperature coefficient i d = 250 a, referenced to 25 o c-39-mv/ o c i dss zero gate voltage drain current v ds = 60v, v gs = 0v - - 1 a i gss gate to body leakage current v gs = 20v, v ds = 0v - - 100 na v gs(th) gate threshold voltage v gs = v ds , i d = 250 a2.5-4.5v r ds(on) static drain to source on resistance v gs = 10v, i d = 50a - 3.01 3.7 m g fs forward transconductance v ds = 10v, i d = 50a - 108 - s c iss input capacitance v ds = 37.5v, v gs = 0v f = 1mhz - 4550 5915 pf c oss output capacitance - 1060 1380 pf c rss reverse transfer capacitance - 30.2 45 pf c oss (er) energy releted output capacitance v ds = 37.5v, v gs = 0v - 1702 - pf q g(tot) total gate charge at 10v v ds = 37.5v, i d = 50a v gs = 0v to 10v (note 4) - 76.8 100 nc q gs gate to source gate charge - 27.5 - nc q gd gate to drain ?miller? charge - 17.4 - nc v plateau gate plateau volatge - 5.1 - v q sync total gate charge sync. v ds = 0v, i d = 50a (note 5) - 66.3 - nc q oss output charge v ds = 37.5v, v gs = 0v - 74.6 - nc t d(on) turn-on delay time v dd = 37.5v, i d = 50a v gs = 10v, r gen = 4.7 (note 4) -34.980ns t r turn-on rise time - 20.1 50 ns t d(off) turn-off delay time - 55.3 120 ns t f turn-off fall time - 19.4 49 ns esr equivalent series resistance f = 1mhz - 1.28 - i s maximum continuous drain to source diode forward current - - 100 a i sm maximum pulsed drain to source diode forward current - - 400 a v sd drain to source diode forward voltage v gs = 0v, i sd = 50a - - 1.3 v t rr reverse recovery time v gs = 0v, i sd = 50a di f /dt = 100a/ s - 66.8 - ns q rr reverse recovery charge - 84 - nc notes: 1.r ja is determined with the device mounted on a 1in 2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of fr-4 material. r jc is guaranteed by design while r ca is determined by the user's board design. 2. repetitive rating: pulse width li mited by maximum junction temperature 3. l = 0.3mh, i as = 34.7a, starting t j = 25 c 4. essentially independent of operating temperature typical characteristics 5. see the test circuit in page 8 a. 50 c/w when mounted on a 1 in 2 pad of 2 oz copper. b. 125 c/w when mounted on a minimum pad of 2 oz copper.
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 3 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 typical performance characteristics figure 1. on-region characteristics figure 2. transfer characteristics figure 3. on-resistance variation vs. figure 4. body diode forward voltage drain current and gate vo ltage variation vs. source current and temperature figure 5. capacitance characteristics figure 6. gate charge characteristics 0.1 1 10 1 10 100 400 *notes: 1. 250 s pulse test 2. t c = 25 o c i d , drain current[a] v ds , drain-source voltage[v] v gs = 15.0v 10.0v 8.0v 7.0v 6.5v 6.0v 5.5v 5.0v 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1 10 100 300 -55 o c 150 o c *notes: 1. v ds = 10v 2. 250 s pulse test 25 o c i d , drain current[a] v gs , gate-source voltage[v] 0.20.40.60.81.01.2 1 10 100 400 *notes: 1. v gs = 0v 2. 250 s pulse test 150 o c i s , reverse drain current [a] v sd , body diode forward voltage [v] 25 o c 0 50 100 150 200 250 300 350 400 2.0 2.5 3.0 3.5 4.0 4.5 *note: t c = 25 o c v gs = 20v v gs = 10v r ds(on) [m ], drain-source on-resistance i d , drain current [a] 0.1 1 10 75 10 100 1000 10000 c oss c iss c iss = c gs + c gd (c ds = shorted) c oss = c ds + c gd c rss = c gd *note: 1. v gs = 0v 2. f = 1mhz c rss capacitances [pf] v ds , drain-source voltage [v] 0 20406080 0 2 4 6 8 10 *note: i d = 50a v ds = 15v v ds = 37.5v v ds = 60v v gs , gate-source voltage [v] q g , total gate charge [nc]
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 4 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 typical performance characteristics (continued) figure 7. breakdown voltage variation figure 8. on-resistance variation vs. temperature vs. temperature figure 9. maximum safe oper ating area figure 10. maximum drain current vs. ambient temperature figure 11. eoss vs. drain to source voltage figure 12. unclamped inductive switching capability -80 -40 0 40 80 120 160 0.92 0.96 1.00 1.04 1.08 *notes: 1. v gs = 0v 2. i d = 250 a bv dss , [normalized] drain-source breakdown voltage t j , junction temperature [ o c] -80 -40 0 40 80 120 160 0.6 0.8 1.0 1.2 1.4 1.6 1.8 *notes: 1. v gs = 10v 2. i d = 50a r ds(on) , [normalized] drain-source on-resistance t j , junction temperature [ o c] 25 50 75 100 125 150 0 20 40 60 80 100 120 140 i d , drain current [a] t c , case temperature [ o c] v gs = 10v r jc = 1.2 o c/w 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 1ms 10ms 100ms i d , drain current [a] v ds , drain-source voltage [v] operation in this area is limited by r ds(on) *notes: 1. t a = 25 o c 2. t j = 150 o c 3. single pulse dc 0 1530456075 0 0.6 1.2 1.8 2.4 3.0 e oss , [ j] v ds , drain to source voltage [v] 0.001 0.01 0.1 1 10 100 1000 1 10 100 t j = 25 o c t j = 150 o c t av , time in avalanche (ms) i as , avalanche current (a)
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 5 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 typical performance characteristics (continued) figu re 13. transient thermal response curve 0.01 0.1 1 10 100 1000 0.005 0.01 0.1 1 0.01 0.1 0.2 0.05 0.02 *notes: 1. z ja (t) = 125 o c/w max. 2. duty factor, d= t 1 /t 2 3. t jm - t c = p dm * z jc (t) 0.5 single pulse normalized thermal impedance, z ja rectangular pulse duration [sec] t 1 p dm t 2
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 6 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 gate charge test circuit & waveform resistive switching test circuit & waveforms unclamped inductive switching test circuit & waveforms
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 7 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 peak diode recovery dv/dt test circuit & waveforms dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- dut v ds + _ driver r g same type as dut v gs ? dv/dt controlled by r g ?i sd controlled by pulse period v dd l l i sd 10v v gs ( driver ) i sd ( dut ) v ds ( dut ) v dd body diode forward voltage drop v sd i fm , body diode forward current body diode reverse current i rm body diode recovery dv/dt di/dt d = gate pulse width gate pulse period -------------------------- d = gate pulse width gate pulse period --------------------------
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 8 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 total gate charge qsync. test circuit & waveforms
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 9 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 dimensional outlin e and pad layout
FDMS037N08B n-channel powertrench ? mosfet www.fairchildsemi.com 10 ?2012 fairchild semiconductor corporation FDMS037N08B rev. c1 trademarks the following includes registered and unregistered trademarks and service marks, owned by fairch ild semiconductor and/or its gl obal subsidiaries, and is not intended to be an exhaustive list of all such trademarks. *trademarks of system general corporation, used under license by fairchild semiconductor. disclaimer fairchild semiconductor reserves the right to make changes with out further notice to any products herein to improve reliability, function, or design. fairchild does not assume an y liability arising out of th e application or use of any product or circuit described herein; neither does it convey an y license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild?s wo rldwide terms and conditions , specifically the warranty therein, which covers these products. life support policy fairchild?s products are not authorized fo r use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used here in: 1. life support devices or systems ar e devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a sign ificant injury of the user. 2. a critical component in any com ponent of a life support, device, or system whose failure to perform can be reasonably ex pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms 2cool? 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